About the Project
Building state-aware compute from proof artifacts to customer-representative workload evaluation.
ATOMiK starts from a practical buyer problem: constrained systems often spend too much work moving, scanning, syncing, replaying, or rebuilding state. The useful question is whether one real workload has enough wasted state movement to justify evaluation.
The current proof stack is artifact-bound: formal proof work for audited algebraic statements, a current Zynq UI proof image, Linux userspace-to-FPGA validation, and an AX7020 workload matrix with wins, losses, and caveats.
The goal is to evaluate state-aware execution where it can create measurable value: one workload, one baseline, one painful constraint, and a clear fit/no-fit decision.
From mathematical insight to software, formal proof work, and evidence-labeled hardware artifacts.
Delta-state algebra forms an Abelian group under XOR. Lean4 proof work formalizes core algebraic properties.
Commutativity, associativity, self-inverse, identity. Machine-checked algebra properties; implementation and workload claims remain evidence-labeled.
Python and C SDK paths with pipeline orchestration, delta generators, and public test artifacts. Available on PyPI.
FPGA prototype paths, a current Zynq UI proof image, Linux userspace validation, and synthesis-characterized scaling are documented with claim boundaries.
Every milestone built on the one before it.
Lean4 proof work covering core Abelian group properties: commutativity, associativity, self-inverse, identity. Implementation and workload claims remain evidence-labeled.
Python and C software paths with public test artifacts, pipeline orchestration, delta generators, and evaluation-oriented tooling.
First FPGA proof: ATOMiK core integrated with PicoRV32 RISC-V on a Tang Nano 9K. Repeat clock and throughput figures only from the linked hardware-validation artifacts.
Built a custom 64-bit RISC-V CPU with native ATOMiK ISA extensions. Delta operations became first-class instructions, not MMIO.
1280x720@60Hz HDMI output on a $13.50 FPGA. Delta-driven display pipeline. Multi-node convergence remains a historical hardware artifact, not a current customer proof claim.
Synthesis-characterized Xilinx Zynq XC7Z020 scaling path with single-bank and parallel-bank resource notes. Use the hardware proof map for claim labels.
atomik-core on PyPI. Commercial licensing and design-partner evaluation are scoped around real workloads and evidence boundaries.
ASIC feasibility planning is underway. The next step is external review before any tape-out commitment.
Inventor & Founder
Matt Rockwell is a systems engineer and founder of ATOMiK, with deep experience in embedded systems, FPGA development, and formal verification. He created the delta-state algebra and built the software, proof, and hardware artifacts that now support ATOMiK's state-aware evaluation path.
Designed the delta-state algebra, built formal proof work, developed hardware prototypes, and published software tooling. ATOMiK is currently founder-led, with the next diligence phase focused on customer-representative workload proof, ASIC/IP review, financial diligence, and partner validation.
ATOMiK began with a simple question: what if we never needed to copy state at all?
Traditional computing wastes enormous resources moving data that hasn't changed. Delta-state algebra addresses this by design — tracking only what changes, with formal proof work around the core algebra.
From formal proof work to FPGA prototype paths and a live Zynq Desk proof image, ATOMiK is the result of building from first principles while labeling each proof boundary.
From artifact-bound proof to customer-representative workload validation and ASIC/IP feasibility review.
View Validation Roadmap→