Validation Roadmap

From proof artifacts to customer workload evidence

ATOMiK's proof stack is evidence-labeled: formal proof work, live hardware UI evidence, Linux userspace-to-FPGA validation, AX7020 workload measurements, and a roadmap toward customer-representative validation.

Formal Work

Labeled

Direct statements only

Zynq UI

v0.39-K

Hardware-validated UI artifact

Linux Path

16/16

Algebraic checks passing

ASIC/IP Path

Feasibility

Roadmap, not measured

FPGA Scaling Evidence

Zynq rows summarize synthesis-characterized FPGA scaling. The ASIC row is a feasibility review target, not a measured or promised result.

N=1
Synthesis row · 444 MHz · 302 LUTEvidence
N=16
Synthesis row · 267 MHz · 941 LUTEvidence
N=512
Synthesis ceiling · 136 MHz · 23,542 LUTEvidence
ASIC path
Feasibility review · Not quoted · Not quoted LUT

Development Timeline

Each phase keeps measured hardware, synthesis output, and roadmap work separated.

✓
Phase 0Validated

Mathematical Foundation

  • ▸Formal proof work covering delta-state algebra properties; public counts are not quoted unless audited across repo, site, and deck
  • ▸Abelian group: commutative, associative, self-inverse, identity
  • ▸Security-sensitive implications remain scoped review targets, not public security claims
Proof-labeled algebra foundation
FORMAL_PROOF / SOFTWARE_VALIDATED proof map
✓
Phase 1Validated

Gowin FPGA — Tang Nano 9K

  • ▸Custom RV64I CPU + ATOMiK ISA extensions on GW1NR-9K
  • ▸1280×720 @60 Hz HDMI output from a $13.50 FPGA
  • ▸Multi-node delta streaming: dual-SoC convergence demonstrated in historical hardware artifacts
  • ▸Historical validation matrix: 53/54 compliance, 9/9 ATOMiK, 10/10 integration, 6/6 display tests
Historical hardware artifact
HARDWARE_VALIDATED proof boundary
✓
Phase 2Validated

Xilinx Zynq XC7Z020 — Parallel Scaling + Linux

  • ▸SYNTHESIS_VALIDATED N=512 config: 23,542 LUT at 136 MHz
  • ▸SYNTHESIS_VALIDATED scaling: 3.7x LUT growth for 16x throughput
  • ▸Linux 6.9 userspace validation: 16/16 PASS via /dev/mem mmap (S-mode, MMU)
  • ▸HARDWARE_VALIDATED Linux userspace path: user process -> kernel -> Wishbone CSR -> ATOMiK core
Synthesis scaling + Linux userspace validated
SYNTHESIS_VALIDATED artifactHARDWARE_VALIDATED Linux proof
4
Phase 3In Progress

ASIC/IP Feasibility Review

  • ▸Open-source PDK review path before any tape-out commitment
  • ▸Gate-count, timing, and power estimates require external review
  • ▸Review whether delta-state algebra maps cleanly into silicon IP
  • ▸Toolchain plan: OpenLane 2, Magic, KLayout, and mentor review
Feasibility review target
5
Phase 4Planned

Strategic Silicon Partner Path

  • ▸Strategic foundry or chip-company diligence when proof gates justify it
  • ▸SRAM compiler integration for on-die state tables
  • ▸Multi-bank ASIC with dedicated on-die interconnect
  • ▸High-throughput custom-silicon direction; numbers remain roadmap until measured
6
Phase 5Planned

Volume ASIC — Edge + Data-Center SKUs

  • ▸Edge SKU direction: power- and area-conscious silicon IP, not a measured silicon claim
  • ▸Infrastructure SKU direction: high parallelism and attach options remain roadmap until measured
  • ▸Security-sensitive hardware directions require separate review before public claims
  • ▸Power and throughput targets require post-review projections and measured silicon before public quoting

Interested in ATOMiK IP?

ATOMiK is preparing investor, chip-partner, and design-partner diligence around state-aware compute. Get in touch to discuss proof review, workload evaluation, licensing, or integration.

Discuss Licensing / Evaluation

Use the evaluation form to anchor on workload, proof boundary, and timeline.

Questions about our timeline? Contact us